View DS1339U-2_1518447.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 of 20 general description the ds1339 serial real - time clock (rtc) is a low - power clock/date device with two programmable time - of - day alarms and a programmable square- wave output. address and data are transferred serially through an i 2 c bus. the clock/date provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 2 4 - hour or 12- hour format with am/pm indicator. the ds1339 has a built - in power - sense circuit that detects power failures and automatically switches to the backup supply, maintaining time, date, and alarm operation. applications handhelds (gps, pos terminal s) consumer electronics (set - top box, digital recording, network appliance) office equipment (fax/printers, copier) medical (glucometer, medicine dispenser) telecommunications (routers, switches, servers) other (utility meter, vending machine, thermostat, modem ) features ? real - time clock (rtc) counts seconds, minutes, hours, day, date, month, and year with leap - year compensation valid up to 2100 ? available in a surface - mount package with an integrated crystal (ds1339c) ? i 2 c serial interface ? two time -of - day al arms ? programmable square - wave output ? oscillator stop flag ? automatic power - fail detect and switch circuitry ? trickle - charge capability ? underwriters laborator ies (ul) recognized pin configurations appear at end of data sheet. ordering information part tem p range voltage (v) pin - package top mark ? ds1339c - 2# - 40c to +85c 2.0 16 so (300 mils) ds1339c - 2 ds1339c - 3# - 40c to +85c 3.0 16 so (300 mils) ds1339c - 3 ds1339c - 33# - 40c to +85c 3.3 16 so (300 mils) ds1339c - 33 ds1339u - 2+ - 40c to +85c 2.0 8 sop 1339 rr - 2 ds1339u - 3+ - 40c to +85c 3.0 8 sop 1339 rr - 3 ds1339u - 33+ - 40c to +85c 3.3 8 sop 1339 rr - 33 + denotes a lead (pb) - free/rohs - compliant package . # denotes a rohs - compliant device that may include lead that is exempt under the rohs req uirements. the lead finish is jesd97 category e3, and is compatible with both lead - based and lead - free soldering processes. ? a ?+? anywhere on the top mark indicates a lead (pb) - free device. a ?#? denotes a rohs - compliant device. rr = second line, revisio n code ds1339 i 2 c serial real - time clock 19 - 5770; rev 4/11
ds1339 i 2 c serial real - time clock 2 of 20 absolute maximum rat ings voltage range on any pin relative to ground???????????????????????? - 0.3v to +6.0v operating temperature range (noncondensing)??????????????????????. - 40c to +85c storage temperature range??????????????????????????????.. -55 c to +125c lead temperature (soldering, 10s) . . .???????????????????????????????+260 c soldering temperature (reflow) . ?????? ???????????????????????????. +260 c stresses beyond those l isted under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) sop junction -to - ambient thermal resistance ( ja ). ???????...???????????????. 206.3 c/w junction -to - case thermal resistance ( jc )????????? ????????????????? 42 c/w so junction -to - ambient thermal resistance ( ja ). ???? ????????????????????. 7 3 c/w junction -to - case thermal resistance ( jc )????????? ????????????????? 23 c/w note 1: package thermal resistances were obtained using the method described in jedec specification jesd51 - 7, using a four - layer board. for detailed information on package thermal consideration s, refer to www.maxim - ic.com/thermal - tutorial . recommended dc opera ting conditions (t a = - 40c to +85c) (note 2 ) parameter symbol conditions min typ max units supply voltage v cc ds1339 -2 1.8 2.0 5.5 v ds1339 -3 2.7 3.0 5.5 ds1339 -33 2.97 3.3 5.5 backup supply voltage v backup 1.3 3.0 3.7 v logic 1 v ih 0.7 x v cc v cc + 0.3 v logic 0 v il - 0.3 +0.3 x v cc v power - fail voltage v pf ds1339 -2 1.58 1.70 1.80 v ds1339 -3 2.45 2.59 2.7 0 ds1339 -33 2.70 2.85 2.97
ds1339 i 2 c serial real - time clock 3 of 20 dc electrical charac teristics (v cc = min to max, t a = - 40c to +85c.) (note 2 ) parameter symbol conditions min typ max units input leakage i li (note 3 ) 1 a i/o leakage i lo (note 4 ) 1 a logic 0 out v ol = 0.4v; v cc > v cc min ( - 3, - 33); v cc 2.0v ( -2) i ol (note 4 ) 3 ma logic 0 out v ol = 0.2 (v cc ); 1.8v < v cc < 2.0v (ds1339 -2) i ol (note 4 ) 3 ma logic 0 out v ol = 0.2 (v cc ); 1.3v < v cc < 1.8v (ds1339 -2) i ol (note 4 ) 250 a v cc active current i cca (note 5 ) 450 a v cc standby current (note 6) i ccs - 2: v cc = 2.2 v 60 100 a - 3: v cc = 3.3 v 80 150 - 33: v cc = 5.5v 200 trickle - charger resistor register 10h = a5h, v cc = typ, v backup = 0v r1 (note 7 ) 250 ? trickle - charger resistor register 10h = a6h, v cc = typ, v backup = 0v r2 2000 ? trickle - charger resistor register 10h = a7h, v cc = typ, v backup = 0v r3 4000 ? v backup leakage current i bklkg 25 100 na dc electrical charac teristics (v cc = 0v, t a = - 40c to +85c. ) (note 2 ) parameter symbol conditions min typ max units v backup current eosc = 0, sqw off i bkosc (note 8 ) 400 700 na v backu p current eosc = 0, sqw on i bksqw (note 8 ) 600 1000 na v backup current eosc = 1 i bkdr 10 100 na
ds1339 i 2 c serial real - time clock 4 of 20 ac electrical charac teristics (v cc = min to max, t a = - 40c to +85c.) (note 9 ) parameter symbol condition min typ max units scl clock frequency f scl fast mode 100 400 khz standard mode 100 bus free time between a stop and start condition t buf fast mode 1.3 s standard mode 4.7 hold time (repeated) start condition (note 10) t hd:sta fast mode 0.6 s standard mode 4.0 low period of scl clock t low fast mode 1.3 s standard mode 4.7 high period of scl clock t high fast mode 0.6 s standard mode 4.0 setup time for a repeated start condition t su:sta fast mode 0.6 s standard mode 4.7 data hold time (notes 1 1 , 12) t hd:dat fast mode 0 0.9 s standard mode 0 data setup time (note 13) t su:dat fast mode 100 ns standard mode 250 rise time of both sda and scl signals (note 1 4 ) t r fast mode 20 + 0.1c b 300 ns standard mode 20 + 0.1c b 1000 fall time of both sda and scl signals (note 1 4 ) t f fast mode 20 + 0.1c b 300 ns standard mode 20 + 0.1c b 300 setup time for stop condition t su:sto fast mode 0.6 s standard mode 4.0 capacitive load for each bus line (note 1 4 ) c b 400 pf i/o capacita nce (sda, scl) c i/o (note 9 ) 10 pf oscillator stop flag (osf) delay t osf (note 15) 100 ms
ds1339 i 2 c serial real - time clock 5 of 20 power- up/down characterist ics (t a = -40 c to +85c) (note 2 , figure 1 ) parameter symbol conditions min typ max un its recovery at power -up t rec (note 16) 2 ms v cc fall time; v pf(max) to v pf(min) t vccf 300 s v cc rise time; v pf(min) to v pf(max) t vccr 0 s warning: under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery - backup mode. note 2 : limits at - 40c are guaranteed by design and are not production tested. note 3 : scl only. note 4 : sda and sqw/ int . note 5 : i cca ? scl at f sc max, v il = 0.0v, v ih = v cc , trickle charger disabled. note 6 : specified with the i 2 c bus inactive, v il = 0.0v, v ih = v cc , trickle charger disabled. note 7 : v cc must be less than 3.63v if the 250 ? resistor is selected. note 8 : using recommended crystal on x1 and x2. n ote 9 : guaranteed by design ; n ot production tested. note 10 : after this period, the first clock pulse is generated. note 11: a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. note 1 2 : the maximum t hd:dat need only be met if the device does not stretch the low period (t low ) of the scl signal. note 1 3 : a fast - mode device can be used in a standard - mode system, but the requirement t s u:dat to 250ns must then be met. this is automatically the case if the device does not stretch the low period of th e scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r(max) + t s u:dat = 1000 + 250 = 1250ns before the scl line is released. note 1 4 : c b ? total capacitance of one bus line in pf. note 1 5 : the parameter t osf is the period of time the oscillator must be stopped for the osf flag to be set over the voltage range of 0.0v v cc v ccmax and 1.3v v backup 3.7v. note 1 6 : this delay applies only if the oscillator is running. if the oscillator is disabled or stopped, no power - up delay occurs. figure 1 . power - up/down timing outputs v cc v pf(max) v pf(min) inputs high - z don't care valid recognized recognized valid t vccf t vccr t rec
ds1339 i 2 c serial real - time clock 6 of 20 figure 2 . timing diagram figure 3 . block diagram alarm, trickle charge, and control registers serial bus interface and address register control logic 1hz 1hz/4.096khz/8.192khz/32.768khz mux/ buffer user buffer (7 bytes) clock and calendar registers power control x 1 c l c l x 2 ds1339 sqw/ int v cc v backup scl sda gnd oscillator and divider "c" version only n
ds1339 i 2 c serial real - time clock 7 of 20 typical operating ch aracteristics (v cc = 3.3v, t a = +25c, unless otherwise noted.) i backup vs. v backup 300 350 400 450 500 550 600 650 700 750 800 850 900 1.3 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v backup (v) supply current (na v cc =0v rs1=rs0=1 i batosc2 ( sqwe = 1 ) i batosc 1 ( sqwe = 0 ) i backup vs. temperature v backup = 3.0v 300 350 400 450 500 550 600 650 -40 -20 0 20 40 60 80 temperature (c) supply current (na v cc =0v intcn = 0 rs2 = rs1 = 1 intcn = 0 i cc vs. v cc 50 100 150 200 250 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 v cc (v) supply current (ua scl=400khz i cca scl=sda =0hz i ccs oscillator frequency vs. supply voltage 32768.0 32768.1 32768.2 32768.3 32768.4 32768.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 oscillator supply voltage (v) frequency (hz)
ds1339 i 2 c serial real - time clock 8 of 20 pin description pin name function sop so 1 ? x1 connection s for standard 32.768khz quartz crystal. the internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (c l ) of 6pf. an external 32.768khz oscillator can also drive the ds1339. in this configuration, the x1 p in is connected to the external oscillator signal and the x2 pin is left unconnected . for more information about crystal selection and crystal layout considerations, refer to application note 58: crystal considerations with dallas real - time clocks . 2 ? x2 3 14 v backup secondary power supply. supply voltage must be held between 1.3v and 3.7v for proper operation. this pin can be connected to a primary cell, such as a lithium button cell. additionally, this pin can be connected to a rechargeable ce ll or a super cap when used in conjunction with the trickle - charge feature. diodes should not be placed in series between the backup source and the v backup input, or improper operation will result. if a backup supply is not required, v backup must be ground ed. ul recognized to ensure against reverse charging current when used with a lithium cell. for more information, visit www.maxim - ic.com/qa/info/ul . 4 15 gnd ground. dc power is provided to the device on these pins. 5 16 sda serial data input/output. sda is the input/output pin for the i 2 c serial interface. the sda pin is an open - drain output and requires an external pullup resistor. the pull up voltage may be up to 5.5v regardless of the voltage on v cc . 6 1 scl serial clock input. scl is used to synchronize data movement on the i 2 c serial interface. the pull up voltage may be up to 5.5v regardless of the voltage on v cc . 7 2 sqw/ int square - wave/interrupt output. programmable square - wave or interrupt outp ut signal. the sqw/ int pin is an open - drain output and requires an external pullup resistor. the pull up voltage may be up to 5.5v regardless of the voltage on v cc . if not used, this pin may be left unconnected . 8 3 v cc primary power supply. when voltage is applied within normal limits, the device is fully accessible and data can be written and read. when a backup supply is connected and v cc is below v pf , reads and writes are inhibited. the timekeeping and alarm functions operate when the device i s powered by v cc or v backup . ? 4 ? 13 n.c. no connection. these pins are unused and must be connected to ground. typical operating ci rcuit ds1339 4 cpu vcc vcc vcc 5 6 8 1 2 sda scl gnd x2 x1 vcc rpu rpu crystal sqw/int v backup 3 7 i
ds1339 i 2 c serial real - time clock 9 of 20 detailed description the ds1339 serial real - time clock (rtc) is a low - power clock/date device with t wo programmable time -of - day alarms and a programmable square - wave output. address and data are transferred serially through an i 2 c bus. the clock/date provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the mont h is automatically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24 - hour or 12- hour format with am/pm indicator. the ds1339 has a built - in power - sense circuit that detects power failures and automatically switches to the backup supply, maintaining time, date, and alarm operation. operation the ds1339 operates as a slave device on the serial bus. access is obtained by implementing a start condition and providing a device identification cod e followed by data. subsequent registers can be accessed sequentially until a stop condition is executed. the device is fully accessible and data can be written and read when v cc is greater than v pf . however, when v cc falls below v pf , the internal clock re gisters are blocked from any access. if v pf is less than v backup , the device power is switched from v cc to v backup when v cc drops below v pf . if v pf is greater than v backup , the device power is switched from v cc to v backup when v cc drops below v backup . the registers are maintained from the v backup source until v cc is returned to nominal levels. the block diagram in figure 3 shows the main elements of the serial real - time clock. power control the power - control functio n is provided by a precise, temperature- compensated voltage reference and a comparator circuit that monitors the v cc level. the device is fully accessible and data can be written and read when v cc is greater than v pf . however, when v cc falls below v pf , the internal clock registers are blocked from any access. if v pf is less than v backup , the device power is switched from v cc to v backup when v cc drops below v pf . if v pf is greater than v backup , the device power is switched from v cc to v backup when v cc drops b elow v backup . the registers are maintained from the v backup source until v cc is returned to nominal levels ( table 1 ). after v cc returns above v pf , read and write access is allowed after t rec ( figure 1 ). on the first application of power to the device the time and date registers are reset to 01/01/00 01 00:00:00 (mm/dd/yy dow hh:mm:ss). table 1 . power control supply condition read/write access powered by v cc < v pf , v cc < v backup no v backup v cc < v pf , v cc > v backup no v cc v cc > v pf , v cc < v backup yes v cc v cc > v pf , v cc > v backup yes v cc oscillator circuit the ds1339 uses an external 32.768khz crystal. the oscillator circuit does not require any ex ternal resistors or capacitors to operate. table 2 specifies several crystal parameters for the external crystal. figure 3 shows a functional schematic of the oscillator cir cuit. the startup time is usually less than 1 second when using a crystal with the specified characteristics.
ds1339 i 2 c serial real - time clock 10 of 20 table 2 . crystal specifications* parameter symbol min typ max units nominal frequency f o 32.768 khz series resistance esr 50 k? load capacitance c l 6 pf *the crystal, traces, and crystal input pins should be isolated from rf generating signals. refer to application note 58: crystal considerations for dallas real - time clocks for additional specifications. clock acc uracy the accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed . additional error is added by crysta l frequency drift caused by temperature shifts. external circuit noise coupled into the oscillator circuit may result in the clock running fast. figure 4 shows a typical pc board layout for isolating the crystal an d oscillator from noise. refer to application note 58: crystal considerations with dallas real - time clocks for detailed information ds1339c only the ds1339c integrates a standard 32,768hz crystal in the package. typical accuracy at nominal v cc and +25c i s approximately 10ppm. refer to application note 58 for information about crystal accuracy vs. temperature. figure 4 . typical pc board layout for crystal local ground plane (layer 2) crystal x1 x2 gnd note: avoid routing signals in the crosshatched area (upper left - hand quadrant) of the package unless there is a ground plane between the signal line and the package.
ds1339 i 2 c serial real - time clock 11 of 20 address map table 3 sh ows the address map for the ds1339 registers. during a multibyte access, when the address pointer reaches the end of the register space (10h), it wraps around to location 00h. on an i 2 c start, stop, or address pointer incrementing to location 00h, the curr ent time is transferred to a second set of registers. the time information is read from these secondary registers, while the clock may continue to run. this eliminates the need to re - read the registers in case of an update of the main registers during a read. table 3 . t imekeeper registers address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function range 00h 0 10 seconds seconds seconds 00? 59 01h 0 10 minutes minutes minutes 00? 59 02h 0 12/ 24 am /pm 10 hour hour hours 1 ? 12 +am/pm 00 ? 23 20 hour 03 h 0 0 0 0 0 day day 1 ? 7 04 h 0 0 10 date date date 01 ? 31 05h century 0 0 10 month month month/ century 01 ? 12 + century 06h 10 year year year 00? 99 07h a1m1 10 seconds seconds alarm 1 seconds 00? 59 08h a1m2 10 m inutes minutes alarm 1 minutes 00? 59 09h a1m3 12/ 24 am /pm 10 hour hour alarm 1 hours 1 ? 12 + am/pm 00 ? 23 20 hour 0a h a1m4 dy/dt 10 date day, date alarm 1 day, alarm 1 date 1 - 7, 1 - 31 0b h a2m2 10 minutes minutes alarm 2 minutes 00? 59 0c h a2 m3 12/ 24 am /pm 10 hour hour alarm 2 hours 1 ? 12 + am/pm 00 ? 23 20 hour 0d h a2m4 dy/ dt 10 date day, date alarm 2 day, alarm 2 date 1 ? 7, 1 ? 31 0e h eosc 0 bbsqi rs2 rs1 intcn a2ie a1ie control ? 0f h osf 0 0 0 0 0 a2f a1f status ? 10h tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 trickle charger ? note: unless otherwise specified, the state of the registers are not defined when power is first applied or when v cc and v backup falls below the v backup(min) .
ds1339 i 2 c serial real - time clock 12 of 20 time and date operat ion the time and date infor mation is obtained by reading the appropriate register bytes. table 3 shows the rtc registers. the time and date are set or initialized by writing the appropriate register bytes. the contents of the time and date r egisters are in the bcd format. the ds1339 can be run in either 12 - hour or 24- hour mode. bit 6 of the hours register is defined as the 12 - or 24 - hour mode- select bit. when high, the 12- hour mode is selected. in the 12- hour mode, bit 5 is the am /pm bit with logic high being pm. in the 24 - hour mode, bit 5 is the 20- hour bit (20 to 23 hours). all hours values, including the alarms, must be re - entered whenever the 12/ 24- hour mode bit is changed. the century bit (bit 7 of the month register) is toggled when the years register overflows from 99 to 00. the day -of - week register increments at midnight. values that correspond to the day of week are user - defined, but must be sequential (i.e., if 1 equals sunday, then 2 equals monday and so on). illogical time and date entries result in undefined operation. when reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. when reading the time and date registers, the user buffers are syn chronized to the internal registers on any start or stop , and when the address pointer rolls over to zero. the countdown chain is reset whenever the seconds register is written. write transfers occurs on the acknowledge pulse from the device. to avoid roll over issues, once the countdown chain is reset, the remaining time and date registers must be written within one second. if enabled, the 1hz square - wave output transitions high 500ms after the seconds data transfer, provided the oscillator is already runni ng. alarms the ds1339 contains two time of day/date alarms. alarm 1 can be set by writing to registers 07h to 0ah. alarm 2 can be set by writing to registers 0bh to 0dh. the alarms can be programmed (by the alarm enable and intcn bits of the control regis ter) to activate the sqw/ int output on an alarm match condition. bit 7 of each of the time of day/date alarm registers are mask bits ( table 4 ). when all the mask bits for each alarm are logic 0, an alarm only occurs when the values in the timekeeping registers 00h to 06h match the values stored in the time of day/date alarm registers. the alarms can also be programmed to repeat every second, minute, hour, day, or date. table 4 shows the possible settings. configurations not listed in the table result in illogical operation. the dy/ dt bits (bit 6 of the alarm day/date registers) control whether the alarm value stored in bits 0 to 5 of that register reflects the day of the week or the date of the month. if dy/ dt is written to a logic 0, the alarm is the result of a match with date of the month. if dy/ dt is written to a logic 1, the alarm is the result of a match with day of the week. the device checks for an alarm match once pe r second. when the rtc register values match alarm register settings, the corresponding alarm flag ?a1f? or ?a2f? bit is set to logic 1. if the corresponding alarm interrupt enable ?a1ie? or ?a2ie? is also set to logic 1 and the intcn bit is set to logic 1, the alarm condition activates the sqw/ int ) signal. if the bbsqi bit is set to 1, the int output activates while the part is being powered by v backup . the alarm output remains active until the alarm flag is cleared by the user.
ds1339 i 2 c serial real - time clock 13 of 20 table 4 . alarm mask bits dy/ dt alarm 1 register mask bits (bit 7) alarm rate a1m4 a1m3 a1m2 a1m1 x 1 1 1 1 alarm once per second x 1 1 1 0 alarm when seconds match x 1 1 0 0 alarm when minutes and seconds match x 1 0 0 0 alarm when hours, minutes, and seconds match 0 0 0 0 0 alarm when date, hours, minutes, and seconds match 1 0 0 0 0 alarm when day, hours, minutes, and seconds match dy/ dt alarm 2 register mask bits (bit 7) alarm rate a2m4 a2m3 a2m2 x 1 1 1 alarm once per minute (00 sec. of every min.) x 1 1 0 alarm when minutes match x 1 0 0 alarm when hours and minutes match 0 0 0 0 alarm when date, hours, and minutes match 1 0 0 0 alarm when day, hours, and minutes match special - purpose registers the ds1339 has two additional regis ters (control and status) that control the rtc, alarms, and square - wave output. control register (0eh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 eosc 0 bbsqi rs2 rs1 intcn a2ie a1ie bit 7: enable oscillator (eosc). this bit when set to logic 0 st arts the oscillator. when this bit is set to a logic 1, the oscillator is stopped. this bit is enabled (logic 0) when power is first applied. bit 5: battery - backed square- wave and interrupt enable (bbsqi). this bit when set to a logic 1 enables the squar e wave or interrupt output when v cc is absent and the ds1339 is being powered by the v backup pin. when bbsqi is a logic 0, the sqw/ int pin goes high impedance when v cc falls below the power - fail trip point. this bit is disabled (logic 0) when power is firs t applied. bits 4 and 3: rate select (rs2 and rs1). these bits control the frequency of the square - wave output when the square wave has been enabled. table 5 shows the square - wave frequencies that can be selected with the rs bits. these bits are both set to logic 1 (32khz) when power is first applied. table 5 . sqw/ int output intcn rs2 rs1 sqw/ int output a2ie a1ie 0 0 0 1hz x x 0 0 1 4.096khz x x 0 1 0 8.192khz x x 0 1 1 32.768khz x x 1 x x a1f 0 1 1 x x a2f 1 0 1 x x a2f + a1f 1 1
ds1339 i 2 c serial real - time clock 14 of 20 bit 2: interrupt control (intcn). this bit controls the relationship between the two alarms and the interrupt output pins. when the intcn bit is set to logic 1, a match between the timekeeping registers an d the alarm 1 or alarm 2 registers activate the sqw/ int pin (provided that the alarm is enabled). when the intcn bit is set to logic 0, a square wave is output on the sqw/ int pin. this bit is set to logic 0 when power is first applied. bit 1: alarm 2 inte rrupt enable (a2ie). when set to a logic 1, this bit permits the alarm 2 flag (a2f) bit in the status register to assert sqw/ int (when intcn = 1). when the a2ie bit is set to logic 0 or intcn is set to logic 0, the a2f bit does not initiate an interrupt si gnal. the a2ie bit is disabled (logic 0) when power is first applied. bit 0: alarm 1 interrupt enable (a1ie). when set to logic 1, this bit permits the alarm 1 flag (a1f) bit in the status register to assert sqw/ int (when intcn = 1). when the a1ie bit is set to logic 0 or intcn is set to logic 0, the a1f bit does not initiate an interrupt signal. the a1ie bit is disabled (logic 0) when power is first applied. status register (0fh) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 osf 0 0 0 0 0 a2f a1f bit 7: oscillator stop flag (osf). a logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the validity of the clock and date data. this bit is edge triggered and is set to logic 1 when the oscillator stops. the following are examples of conditions that can cause the osf bit to be set: 1) the first time power is applied. 2) the voltage on both v cc and v backup are insufficient to support oscillation. 3) the eosc bit is turned off. 4) external influences on the crystal (e.g., noise, leakage, etc.). this bit remains at logic 1 until written to logic 0. this bit can only be written to a logic 0. bit 1: alarm 2 flag (a2f). a logic 1 in the alarm 2 flag bit indicates that the time matched the ala rm 2 registers. if the a2ie bit is a logic 1 and the intcn bit is set to a logic 1, the sqw/ int pin is also asserted. a2f is cleared when written to logic 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged . bit 0: alarm 1 flag (a1f). a logic 1 in the alarm 1 flag bit indicates that the time matched the alarm 1 registers. if the a1ie bit is a logic 1 and the intcn bit is set to a logic 1, the sqw/ int pin is also asserted. a1f is cleared when written to logi c 0. this bit can only be written to logic 0. attempting to write to logic 1 leaves the value unchanged.
ds1339 i 2 c serial real - time clock 15 of 20 trickle charger register (10h) the simplified schematic in figure 5 shows the basic components of the trickl e charger. the trickle - charge select (tcs) bits (bits 4 to 7) control the selection of the trickle charger. to prevent accidental enabling, only a pattern on 1010 enables the trickle charger. all other patterns disable the trickle charger. the trickle char ger is disabled when power is first applied. the diode - select (ds) bits (bits 2 and 3) select whether or not a diode is connected between v cc and v backup . the rout bits (bits 0 and 1) select the value of the resistor connected between v cc and v backup . table 6 shows the bit values. table 6 . trickle charger register (10h) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 x x x x 0 0 x x disabled x x x x 1 1 x x disabled x x x x x x 0 0 disabled 1 0 1 0 0 1 0 1 no diode, 250 ? resistor 1 0 1 0 1 0 0 1 one diode, 250 ? resistor 1 0 1 0 0 1 1 0 no diode, 2k ? resistor 1 0 1 0 1 0 1 0 one diode, 2k ? resistor 1 0 1 0 0 1 1 1 no diode, 4k ? resistor 1 0 1 0 1 0 1 1 one diode, 4k ? resistor 0 0 0 0 0 0 0 0 initial power - up values warning: the rout value of 250 ? must not be selected whenever v cc is greater than 3.63v. the user determines diode and resistor selection according to the maximum current desired for battery or super cap charging. the maximum charging current can be calculated as illustrated in the following example. assume that a 3.3v system power supply is applied to v cc and a super cap is connected to v backup . also assume that the trick le charger has been enabled with a diode and resistor r2 between v cc and v backup . the maximum current i max would therefore be calculated as follows: i max = (3.3v - diode drop) / r2 (3.3v - 0.7v) / 2k ? 1.3ma as the super cap or battery charges, the vo ltage drop between v cc and v backup decreases and therefore the charge current decreases.
ds1339 i 2 c serial real - time clock 16 of 20 figure 5 . programmable trickle charger i 2 c serial data bus the ds1339 supports the i 2 c bus protocol. a device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. the device that controls the message is called a master. the devices that are controlled by the master are referred to as slaves. the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the ds1339 operates as a slave on the i 2 c bus. within the bus specifications, a standard mode (100khz cycle rate) and a fast mode ( 400khz cycle rate) are defined. the ds1339 works in both modes. connections to the bus are made via the open- drain i/o lines sda and scl. the following bus protocol has been defined ( figure 6 ): ? data transfer may b e initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high are interpreted as control signals. accordingly, the following bus con ditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line, from high to low, while the clock is high, defines a start condition. stop data transfer: a change in the state of the data line, from low to high, while the clock line is high, defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is stable for the duration of the high period of the cl ock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. 1 of 16 select note: only 1010 enables charger 1 of 2 select 1 of 3 select tcs3 tcs2 tcs1 tcs0 ds1 ds0 rout1 rout0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 250 ? 2k ? 4k ? r1 r3 r2 trickle charge register tcs 0 - 3 = trickle charger select ds 0 - 1 = diode select rout 0 - 1 = resistor select v cc v backup
ds1339 i 2 c serial real - time clock 17 of 20 each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes tra nsferred between start and stop conditions is not limited, and is determined by the master device. the information is transferred byte - wise and each receiver acknowledges with a ninth bit. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the l ast byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. figure 6 . data transfer on i 2 c serial bus depending upon the state of the r/ w bit, two types of data transfer are possible: 1) data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next follows a number of data bytes. the slave returns an acknowledge bit af ter each received byte. data is transferred with the most significant bit (msb) first. 2) data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. this is followed by the slave transmitting a number of data bytes. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a ?not acknowledge? is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. dat a is transferred with the most significant bit (msb) first. the ds1339 can operate in the following two modes: 1) slave receiver mode (write mode): serial data and clock are received through sda and scl. after each byte is received an acknowledge bit is tra nsmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address recognition is performed by hardware after reception of the slave address and direction bit ( figure 7 ). the s lave address byte is the first byte received after the start condition is generated by the master. the slave address byte contains the 7 - bit ds1339 address, which is 1101000, followed by the direction bit (r/ w ), which is 0 for a write. after receiving and decoding the slave address byte the slave outputs an acknowledge on the sda line. after the ds1339 acknowledges the slave address + write bit, the master transmits a register address to the ds1339. this
ds1339 i 2 c serial real - time clock 18 of 20 sets the register pointer on the ds1339, with the ds1 339 acknowledging the transfer. the master may then transmit zero or more bytes of data, with the ds1339 acknowledging each byte received. the address pointer increments after each data byte is transferred. the master generates a stop condition to terminat e the data write. 2) slave transmitter mode (read mode): the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit indicates that the transfer direction is reversed. serial data is transmitted on sda by th e ds1339 while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer ( figure 8 ). the slave address byte is the first byte received after the start condition is generated by the master. the slave address byte contains the 7 - bit ds1339 address, which is 1101000, followed by the direction bit (r/ w ), which is 1 for a read. after receiving and decoding the slave address byte the slave outputs an acknowled ge on the sda line. the ds1339 then begins to transmit data starting with the register address pointed to by the register pointer. if the register pointer is not written to before the initiation of a read mode the first address that is read is the last one stored in the register pointer. the address pointer is incremented after each byte is transferred. the ds1339 must receive a ?not acknowledge? to end a read. figure 7 . data write ? slave receiver mode figure 8 . data read (from current pointer location) ? slave transmitter mode figure 9 . data read (write pointer, then read) ? slave receive and transmit ... a xxxxxxxx a s 0 xxxxxxxx a xxxxxxxx a xxxxxxxx a p s - start a - acknowledge (ack) p - stop data transferred (x+1 bytes + acknowledge) 1101000 master to slave slave to master ... a xxxxxxxx a 1101000 s 1 xxxxxxxx a xxxxxxxx xxxxxxxx a p a s - start a - acknowledge (ack) p - stop a - not acknowledge (nack) data transferred (x+1 bytes + acknowledge) note: last data byte is followed by a nack master to slave slave to master ... a xxxxxxxx xxxxxxxx a xxxxxxxx a xxxxxxxx a p s - start sr - repeated start a - acknowledge (ack) p - stop a - not acknowledge (nack) data transferred (x+1 bytes + acknowledge) note: last data byte is followed by a nack a xxxxxxxx a 1101000 s 0 a 1101000 sr 1 master to slave slave to master
ds1339 i 2 c serial real - time clock 19 of 20 handling, pcb layout , and assembly the ds1339c package contains a quartz tuning - fork crystal. pick-and- place equipment may be used, but precautions should be taken to ensure that excessive shocks are avoided. ultrasonic cleaning should be avoided to prevent damage to the crystal. avoid running signal traces u nder the package, unless a ground plane is placed between the package and the signal line. all n.c. (no connect) pins must be connected to ground. moisture - sensitive packages are shipped from the factory dry - packed. handling instructions listed on the package label must be followed to prevent damage during reflow. refer to the ipc/jedec j - std - 020b st andard for moisture - sensitive device (msd) classifications. pin configurations chip information process: cmos package information for the latest package outline information and land patterns (footprint s ) , go to www.maxim - ic.com/packages . note that a ?+?, ?#?, or ? - ? in the package c ode indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 8 sop u8+1 21-0036 90-0092 16 so w16 # h2 21-0042 90-0107 sop sqw / int x1 x2 gnd v cc scl sda v back up ds1339 top view sqw / int scl sda gnd v back up v cc n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. ds1339c so (300 mils) top view
ds1339 i 2 c serial real - time clock 20 of 20 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 2011 maxim integrated prod ucts maxim is a registered trademark of maxim integrated products, inc. revision history revision date description pages changed 100108 removed leaded part numbers from the ordering information table. 1 removed the pullup resistor voltage spec from the recommended dc operati ng conditions table and added it to the pin descriptions. 2, 8 removed note 7 from the i bkdr specification in the dc electrical characteristics table. 3 updated the block diagram (figure 3) to show that sqw/int is open drain. 6 added the ul link to t he v backup description in the pin description table. 8 removed the duplicate oscillator circuit section. 9 added the initial por state for time and date registers in the power control section. 9 changed the series resistance (esr) value in table 2 fr om 45k ? to 50k ? . 10 added the overbar to the ?a? legend for nack in figure 8. 18 4/11 updated the soldering temperature and added lead temperature information to the absolute maximum ratings section; added the package thermal characteristics section and updated the sop ja and jc numbers; changed the v cc max numbers from 2.2v to 5.5v for ds1339 - 2 and 3.3v to 5.5v for ds1339 - 3 in the recommended dc operating conditions table. 2 updated the i ccs parameter in the dc electrical characteristics table. 3 changed the 10 hour bit to 20 hour bit for 02h, 09h, and 0ch in table 1 and the time and date operation section. 11, 12 updated the handling, pcb layout, and assembly section; removed the transistor count from the chip information section; ad ded the land pattern numbers to the package informatio n table. 19

▲Up To Search▲

Price & Availability of DS1339U-2

	To Download DS1339U-2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .